As liquid crystal televisions have become less expensive in recent years, they are in widespread use among average households. Also, since broadband communications have become widespread, there are more occasions on which moving images are displayed even with personal computers. In addition, since digital terrestrial broadcasting has started, there are more occasions on which moving images are displayed with portable devices such as portable phones.
In view of this, research and development have been widely conducted for improvement of the moving image quality of liquid crystal displays, and such research and development have produced many successful results.
Patent Document 1 discloses one of techniques that are attained as a result of such research and development. The technique of Patent Document 1 is for improvement of the moving image quality of liquid crystal TVs. FIGS. 17 and 18 show the technique of Patent Document 1.
FIG. 17 is a view showing an arrangement of a liquid crystal display 21 disclosed in Patent Document 1. The liquid crystal display 21 includes pixels Aij, each of which includes: a TFT:Qx; an auxiliary capacitor Cs; and a liquid crystal element LC. The TFT:Qx includes: a drain terminal connected with one terminal of the auxiliary capacitor Cs and one terminal of the liquid crystal element LC; a source terminal connected with one of source lines Xj (where j=n−1 to n+2); and a gate terminal connected with one of gate lines Yi (where i=n−1 to n+2). The other terminal of the auxiliary capacitor Cs is connected with one of auxiliary capacitance lines Ci (where j=n−1 to n+2).
The source line Xj is connected with a video signal driver 22. The gate line Yi is connected with a scanning signal driver 23. The auxiliary capacitance line Ci is connected with an auxiliary capacitor driver 24.
In addition, these lines are fed with their respective voltages shown in FIG. 18.
Specifically, the source line Xj is fed with a voltage designated by “VIDEO SIGNAL” in FIG. 18. The gate line Yi is fed with a voltage designated by “SCANNING SIGNAL” in FIG. 18. The auxiliary capacitance line Ci is fed with a voltage designated by “AUXILIARY CAPACITOR LINE SIGNAL” in FIG. 18. This causes a voltage applied to the liquid crystal element LC to be changed as indicated in “PIXEL POTENTIAL CHANGE (VOLTAGE APPLIED TO LIQUID CRYSTAL)” in FIG. 18. Specifically, the liquid crystal is fed with a voltage Vd during the first half of one horizontal period, while the voltage Vd is changed into a voltage Vd′ in the second half. This causes the transmittance of the pixel to change as indicated in “LUMINANCE CHANGE” in FIG. 18.
As described above, Patent Document 1 is arranged such that a period during which the luminance of a pixel is reduced with use of an auxiliary capacitance is provided so as to improve the residual image characteristic exhibited when a moving image is displayed with a pseudo-impulse driving.
As is clear from the relationship between the applied voltages and the luminance change, the liquid crystal used in Patent Document 1 is of a normally while mode (in which the transmittance of the liquid crystal is maximal when no voltage is applied).
The following description deals with a D/A converter circuit suggested for use in liquid crystal display devices, while associating the D/A converter circuit with its production process (see, for example, Patent Documents 2 and 3).
In recent years, there have been in widespread use liquid crystal display devices including polycrystalline silicon thin film transistors (TFTs) such as polysilicon TFTs and continuous grain (CG) silicon TFTs. Particularly, with respect to mobile liquid crystal displays for use in portable phones, personal digital assistants (PDAs), and the like, efforts have been made to reduce the production costs by incorporating a gate driver circuit and a source driver circuit into a liquid crystal panel with use of polycrystalline silicon TFTs.
FIG. 19 is a block diagram showing an arrangement of a conventional liquid crystal display device including polycrystalline silicon TFTs. The display device shown in FIG. 19 includes a TFT substrate (not shown). The display device further includes, on the TFT substrate: a pixel array 80; a gate driver circuit 81; and a source driver circuit 82. The pixel array 80 includes m×n pixel circuits Aij. The gate driver circuit 81 drives gate lines G1 through Gn in accordance with a control signal C1. The source driver circuit 82 drives source lines S1 through Sm in accordance with a control signal C2 and image data DX.
The source driver circuit 82 includes: an m-bit shift register 83; an m×s-bit register 84; an m×s-bit latch 85; and m D/A converter circuits 86. The shift register 83 generates a timing pulse in accordance with the control signal C2. The register 84 sequentially stores s-bit image data DX in accordance with the timing pulse generated by the shift register 83. The m×s-bit image data stored in the register 84 is sent to the latch 85, and then, in the D/A converter circuits 86, is converted into analog voltage signals. This allows voltages corresponding to the image data DX to be fed into the pixel circuits Aij via the source lines S1 through Sm.
There are several types of D/A converter circuits for use in conventional liquid crystal display devices. Patent Document 2 describes D/A converter circuits of a capacitive division type, a resistive division type, and a pulse width modulation (PWM) type (see FIGS. 20 through 22). In a D/A converter circuit of a capacitive division type (FIG. 20), an electric charge is accumulated in each of capacitors C1 through C8 when input switches SW1, each having a terminal to which no voltage is applied, are set in an ON state. Then, when output switches SW2 are set in an ON state, the electric charge accumulated in each of the capacitors C1 through C8 is transferred to a capacitor C9. The capacitors C1 through C8 each have a capacitance which accords with a corresponding one of the respective weights (2w, where w represents an integer of 0 to 7) of bits d1 through d8 of image data. The switches SW2 are individually set either in an ON state or in an OFF state in response to the bits d1 through d8 of image data.
A D/A converter circuit of a resistive division type (FIG. 21) includes a voltage divider including resistors R1 through R8 arranged in series. The voltage divider is provided with voltages VH and VL at its two ends, respectively. The resistors R1 through R8 have their respective nodes which are each connected with a switch SW3. The switches SW3 are individually set either in an ON state or in an OFF state in response to the result (output from a decoder 91) of image data decoding.
A D/A converter circuit of a PWM type (FIG. 22) includes a PWM circuit 93 which generates a pulse having a width corresponding to image data stored in a latch 92. A switch SW4 is set in an ON state while being fed with a pulse from the PWM circuit 93. One terminal of the switch SW4 is fed with a ramp wave voltage from a ramp wave power supply 94. The D/A converter circuits shown in FIGS. 20 through 22 respectively allow a voltage corresponding to image data to be fed into a source line Sj connected with an output terminal Vout.
In liquid crystal display devices in general, there exists a stray capacitance between a gate line Gi and a source line Sj (directly, or indirectly via a TFT in-between). Therefore, simply using one of the D/A converter circuits shown respectively in FIGS. 20 through 22 does not allow the voltage of a source line Sj to reach a desired level within a predetermined period of time. The D/A converter circuit of a capacitive division type shown in FIG. 20, in particular, does not allow the voltage of a source line Sj to reach a desired level regardless of the length of time. This is because only small amounts of electric charge can be accumulated in the capacitors C1 through C8. In view of this, a conventional liquid crystal display device includes, between the output terminal Vout of a D/A converter circuit 95 and a source line Sj, an analog buffer circuit 96 (having an impedance transformation ratio of 1 to 1; also called an op amp) which amplifies an output from the D/A converter circuit 95 (see FIG. 23). This analog buffer circuit is disclosed in Patent Document 3, for example.    [Patent Document 1] Japanese Unexamined Patent Application Publication Tokukai No. 2001-265287; published on Sep. 28, 2001    [Patent Document 2] Japanese Unexamined Patent Application Publication Tokukai No. 2004-199082; published on Jul. 15, 2004    [Patent Document 3] Japanese Unexamined Patent Application Publication Tokukai No. 2003-338760; published on Nov. 28, 2003